时钟偏移（英语：clock skew）或称时钟偏斜，是指时钟信号到达数字电路各个部分所用时间的差异。对于大多数数字集成电路系统，例如计算机系统，各种信号都是根据系统定时器信号的时钟频率进行同步的，这样这些信号就能在相同的步调上工作。最理想的情况是，输入信号在下一个时钟的有效电平或者信号边缘带来之前，切换并在其正确的逻辑电平上保持稳定，从而使整个电路系统的行为合乎预设。在一个完整的电路系统中，不同电子器件的速度可能有着大小不一的差距，因此系统存在一个最大的运行频率。实际上，信号可能并不能准确地在理想的信号边缘到来之前的瞬间保持在其正确的信号值上，它保持稳定所需的时间于理想情况有一定的偏移，这种偏移就是时钟偏移。除了上面这种情况，还有其他多种原因可以导致时钟偏移的现象。

The operation of most digital circuit systems, such as computer systems, is synchronized by a periodic signal known as a "clock" that dictates the sequence and pacing of the devices on the circuit. This clock is distributed from a single source to all the memory elements of the circuit, which are also called registers or flip-flops. In a circuit using edge-triggered registers, when the clock edge or tick arrives at a register, the register transfers the register input to the register output, and these new output values flow through combinational logic to provide the values at register inputs for the next clock tick. Ideally, the input to each memory element reaches its final value in time for the next clock tick so that the behavior of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.