Physical verification

Physical verification is a process whereby an integrated circuit layout (IC layout) design is checked via EDA software tools to see if it meets certain criteria. Verification involves design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), XOR (exclusive OR), and antenna checks.

单词	Physical verification
释义	Physical verification 英语百科 Physical verification Physical verification is a process whereby an integrated circuit layout (IC layout) design is checked via EDA software tools to see if it meets certain criteria. Verification involves design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), XOR (exclusive OR), and antenna checks.
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