高级综合（High-level Synthesis，缩写 HLS），又译高层次综合，另又称C合成（C synthesis）、电子系统层次合成（Electronic System Level synthesis，缩写 ESL synthesis），是将电路设计规范的算法级或行为级描述在一定的约束条件下转化为电路结构描述的方法和过程。高层次综合又称为行为级综合、算法级综合等。它使设计者能够在更高层次进行电子设计，更快速有效地在较高层次设计验证和仿真，而较低层次的工作由工具来自动完成，从而让数字电路系统设计工程师可以有更多的精力和更充分的条件去进行设计空间的搜索，寻求最佳的设计方案。

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages., although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/Matlab. The code is analyzed, architecturally constrained, and scheduled to create a register-transfer level (RTL) hardware description language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.